1. Field of the Invention
The present invention relates to an ESD(Electro-Static Discharge) protection circuit, and more particularly, to an ESD protection circuit and a method for fabricating the same, which has an improved performance.
2. Background of the Related Art
FIG. 1 illustrates a system of a related art ESD protection circuit. In general, a maximum field strength against which an oxide film in an MOS transistor can endure is 6 MV/cm, which corresponds to 30V if the oxide film is scaled up to a thickness of 50 nm. A voltage of this magnitude can be easily generated from minute static electricity occurring around a circuit. There is continuous generation of static electricity when a human body makes movement, and the human body acts as a carrier that carries a great amount of charge. Therefore, if the human body comes close to a conductor, the static electricity is discharged, causing a great amount of current to flow within a short time. Thus, as the amount of charge required to damage a transistor is very small, an ESD protection circuit 2 is provided to an input pin between a pad 1 and a main chip 3 so that the static electricity, rushing into an inner part of the main chip 3, is discharged through an appropriate circuit for maintaining voltages on an input terminal and an output terminal within fixed ranges. Thus, an input protection circuit and an output protection circuit are required for prevention of static breakdown.
A related art ESD protection circuit will be explained with reference to the attached drawings. FIG. 2 illustrates a first exemplary related art ESD protection circuit, and FIG. 3 illustrates a second exemplary related art ESD protection circuit.
Referring to FIG. 2, the first exemplary related art ESD protection circuit is provided with a plurality of first transistors 11 each having a collector connected to an input pin between a pad 1 and a main chip 3, and a gate and an emitter both grounded, wherein a voltage from the pad 1 is provided to the main chip 3 directly in a regular case and an inflow of a static electricity is bypassed to the transistors 11, thereby protecting the main chip 3.
Referring to FIG. 3, the second exemplary related art ESD protection circuit is provided with a plurality of second transistors 12 each having a collector connected to an input pin between a pad 1 and a main chip 3 through a first resistor 13, a gate grounded, and an emitter grounded through a second resistor 14, wherein a voltage from the pad 1 is provided to the main chip 3 directly in a regular case and an inflow of static electricity is bypassed to the transistors 12, thereby protecting the main chip 3.
However, the related art ESD protection circuits and methods for fabricating the same have the following problems.
First, the related art ESD protection circuit, having the plurality of transistors each with the collector connected to the input pin between the pad and the main chip and the gate and the emitter both grounded, i.e., no resistor is connected to the emitter/collector, may be subject to breakage at a particular point caused by momentary concentration of a charge on the particular point in a case of a BJT of single or plural units or in case the static electricity is generated from inside, and a space of the ESD protection circuit for preventing such an occurrence requires a larger area.
Second, the related art ESD protection circuit, having the plurality of transistors each with the collector connected to the input pin between the pad and the main chip through the first resistor, the gate grounded, and the emitter grounded through the second resistor, is involved in reduction of BJT gain caused by the two resistors connected to the emitter/collector and a drop of an ESD capability.
Accordingly, the present invention is directed to an ESD protection circuit and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an ESD protection circuit and a method for fabricating the same, which has an improved performance.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the ESD protection circuit includes a substrate, a transistor formed on the substrate, a first insulating film formed on the substrate inclusive of the transistor and having a first contact hole to an input terminal of transistor, a buffered layer formed on the first insulating film inclusive of the first contact hole and electrically connected to the input terminal for acting as a resistor, a second insulating film formed on the first insulating film inclusive of the buffered layer and having a second contact hole to the buffered layer, and a pad formed on the second insulating film inclusive of the second contact hole and electrically connected to the buffered layer.
In another aspect of the present invention, there is provided a method for fabricating an ESD protection circuit, including the steps of (1) forming a transistor on a substrate, (2) forming a first insulating film on the substrate inclusive of the transistor and having a first contact hole to an input terminal of the transistor, (3) forming a buffered layer in the first contact hole and the first insulating film in the vicinity of the first contact hole, (4) forming a second insulating film on the first insulating film inclusive of the buffered layer and having a second contact hole to the buffered layer, and (5) forming a pad both on the second contact hole and the second insulating film in the vicinity of the second contact hole.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.